🧪 Testing & Binning
Probing every chip electrically and sorting it by quality and speed.
At nanometer scale, defects are statistically unavoidable — a single dust particle or misplaced atom can disable a circuit — so every chip must be tested before it ships. While still on the wafer, fine needle probes (or non-contact pads) touch each die and run millions of electrical patterns through it, checking that every circuit responds correctly. This 'wafer sort' identifies which dies work and marks the dead ones so they are discarded.
The fraction of good dies on a wafer is called yield, and it is one of the most closely guarded numbers in the industry: on a mature process yield can exceed 90%, while a brand-new leading-edge process may start far lower and climb as it matures. Because giant AI chips occupy huge die area, even a few defects per wafer can scrap an expensive chip — which is one reason they cost so much.
Working chips are then 'binned' by performance: every chip is slightly different, so the fastest, most efficient dies are sorted into premium products, while ones that run a bit slower or have a defective core disabled become lower-tier parts. It is the same idea as grading produce — sort by quality, then price and sell each grade for what it's worth.
The science: catching the inevitable defect
At nanometer scale, defects are statistical, not occasional — a stray particle, a void in a wire, or random dopant fluctuation can disable any of billions of transistors. So every die is exercised electrically. During wafer sort, a probe card lowers thousands of fine needles (or non-contact pads) onto each die and an automated tester streams millions of input patterns through it, comparing outputs against the known-good answers. Built-in self-test circuits help the chip test its own memories and logic at full speed. Dies that fail are inked or mapped so they are discarded before the expensive packaging step.
Yield: the industry's most guarded number
The share of good dies per wafer is yield, and it governs the economics of the whole enterprise. A mature process can exceed ~90%; a brand-new leading-edge node may begin far lower and climb for months or years as engineers hunt down systematic defect sources. Because yield directly sets the cost per working chip, fabs treat their numbers as trade secrets.
The hardest challenges and failure modes
Some defects only appear under specific voltage, temperature, or timing, so chips are retested hot and cold and at speed to catch 'marginal' parts that would fail in the field. Test time itself is costly — every extra second multiplied across millions of dies adds up — forcing a constant trade-off between coverage and throughput. The cruelest problem for AI is area: a giant die means a random defect is more likely to land on it, so very large chips suffer disproportionately low yield and high cost.
Binning and why it matters for AI chips specifically
No two transistors are identical, so working dies are binned by speed and power: the best become premium parts, while slower ones or those with a single bad core are sold as lower tiers with that core fused off. This salvage is central to AI-chip economics — partially defective dies still ship as cut-down accelerators rather than being thrown away. Because AI GPUs are enormous and expensive, smart binning and high yield are what make it possible to supply them at all, and they shape which performance grade ends up handling your training versus inference workloads.
Key facts
- Wafer-sort probes run millions of electrical test patterns per die
- 'Yield' = the share of working dies; mature nodes can exceed ~90%
- Big AI dies are hit harder by defects — fewer chips per wafer
- Binning sorts chips by speed/power into premium vs. lower tiers
- Partially-defective chips can ship with cores disabled (salvage)
- Final chips are re-tested after packaging, often at hot and cold extremes
Who & what makes it happen
Teradyne, Advantest (test systems); FormFactor (probe cards); fabs (TSMC, Samsung, Intel) run wafer sort
Terms to know
Tap any term for a plain-English definition.
From silicon to strategy
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